1. Technical Field
The present disclosure relates to the field of semiconductor integrated circuit technology, and more particularly to a semiconductor chip and method of manufacturing the same.
2. Description of the Related Art
As the density in semiconductor integrated circuits increases, it becomes increasingly difficult to fit a large number of transistors onto a single chip. Chip stacking technologies can mitigate the above problem. For example, in three-dimensional integrated circuit (3D-IC) technology, vertical interconnects are formed using a bonding process to connect a plurality of chips, and the density of transistors can be increased by vertically stacking the chips. In addition, 3D-ICs have improved operating speed and reduced power consumption. As such, there has been a strong focus on chip stacking technologies (e.g. 3D-ICs) in recent years.
In current chip stacking technologies, the chips are usually fabricated individually before stacking. As shown in FIG. 1, a chip may include a substrate 10′, a dielectric layer 20′ disposed on the substrate 10′, and a metal pad 30′ disposed in a recess in the dielectric layer 20′. The metal pad 30′ is electrically connected to, for example, devices in the substrate 10′. The metal pad 30′ may also be electrically connected to external electrical components. As shown in FIG. 1, a top surface of the dielectric layer 20′ is located below a top surface of the metal pad 30′. A plurality of chips may be bonded together using, for example, thermocompression bonding, so as to form a stacked chip.
FIG. 2 is a scanning electron microscope (SEM) photograph of a cross-section of a stacked chip in which adjacent metal pads are deformed and connected to each other. During thermocompression bonding, the metal pads deform under the application of heat and pressure. In some instances, adjacent metal pads may deform and contact each other, which may result in shorting within the stacked chip (see dotted circled regions in FIG. 2). As devices scale, the density of the metal pads on the chip increases, which means that the pitch of the metal pads decreases. As the pitch or gap between adjacent metal pads decreases, the likelihood of adjacent metal pads deforming and contacting each other (during thermocompression bonding) increases.
Some methods have been proposed to mitigate the above shorting issue. For example, it has been proposed that reducing a width of the metal pads can increase the gap between adjacent metal pads. However, reducing the width of the metal pads may lower the alignment accuracy of the stacked chip, since it is more difficult to accurately align and bond the metal pads on a top chip and a bottom chip when the size of the metal pads is reduced. In particular, misalignment and poor bonding of the chips may lower the yield of the chip stacking process.